mdComputer8 (2019-09-20)

How a computer works
 
I started this project out of curiosity on how a computer works.
How can logic gates like AND, OR, NAND and NOR be created with nothing more than a few transistors and resistors?
How can you make memory with these logic gates? Do calculations? Control the flow?

It didn't take long to find the excellent YouTube series of Ben Eater in which he explains all this while building a minimalistic computer on a breadboard. This inspired me to build one myself.

After building elementary logic purely based on a few discrete components, I decided just like Ben Eater to build the computer with TI 7400 Logic IC Series from the 70's to save time and space.
Where he used 74LSxx, I went for 74HCxx which are more or less equivalent but much easier to find and consume much less power (<250mA compared to >1A for the whole computer)
Also, I choose not to use breadboards because of price and difficulty to store away without disassembling it.

The final goal for the computer should be to enter a program like calculating prime-numbers in memory and run that successful. To do that Ben Eaters 16 byte memory and 16 instruction computer would not be enough. My target specification are:

- 256 bytes of RAM (8 bit addressing)
- 100+ operation instructions (1 byte operation plus optional byte for operand)
- 4 registers of which one has a decimal/hexadecimal display
- Manual input for programming/listing
- Serial input/output for autoload and terminal programming/listing


To achieve that I used some of James Bates improvements on Ben Eaters design together with some ideas of myself.
 
 


 
 
 
Instruction Set
 
OpcodeMnemonicDescription
00NOPDo nothing
1AMOV A,[adr]/varLoad value in address/variable into A
1BMOV B,[adr]/varLoad value in address/variable into B
1DMOV D,[adr]/varLoad value in address/variable into D
1EMOV OUT, [adr]/varLoad value in address/variable into OUPUT
2AMOV A, val/xxH/'C'
LEA A, var/label
Load value immediate into A
Load variable address into A
2BMOV B, val
LEA B, var/label
Load value immediate into B
Load variable address into B
2DMOV D, val
LEA D, var/label
Load value immediate into D
Load variable address into D
2EMOV OUT, val
LEA OUT, var/label
Load value immediate into OUTPUT
Load variable address into OUTPUT
30MOV A, BLoad B into A
31MOV A, PCLoad PC into A
32MOV A, DLoad D into A
33MOV A, OUTLoad OUTPUT into A
34MOV B, ALoad A into B
35MOV B, PCLoad PC into B
36MOV B, DLoad D into B
37MOV B, OUTLoad OUTPUT into B
38MOV D, ALoad A into D
39MOV D, BLoad B into D
3AMOV D, PCLoad PC into D
3BMOV D, OUTLoad OUTPUT into D
3CMOV OUT, ALoad A into OUTPUT
3DMOV OUT, BLoad B into OUTPUT
3EMOV OUT, PCLoad PC into OUTPUT
3FMOV OUT, DLoad D into OUTPUT
40MOV A, INLoad IN into A
41MOV B, INLoad IN into B
42MOV D, INLoad IN into D
43MOV OUT, INLoad IN into OUT
4AMOV [adr], AStore A in address/variable
4BMOV [adr], BStore B in address/variable
4CMOV [adr], PCStore PC in address/variable
4DMOV [adr], DStore D in address/variable
4EMOV [adr], OUTStore OUTPUT in address/variable
4FMOV [adr], INStore IN in address/variable
50ADD A, [adr]/varLoad value in address/variable into B, A PLUS B to A, FLAGS set
51ADD A, valLoad value immediately into B, A PLUS B to A, FLAGS set
52ADC A, [adr]Load value in address/variable into B, A PLUS B +CARRY to A, FLAGS set
53ADC A, valLoad value immediately into B, A PLUS B +CARRY to A, FLAGS set
54AND A, [adr]Load value in address/variable into B, A AND B to A
55AND A, valLoad value immediately into B, A AND B to A
56INC AIncrement A
5BADD A, BA PLUS B to A, FLAGS set
5CADD A, PCLoad PC to B, A PLUS B to A, FLAGS set
5DADD A, DLoad D to B, A PLUS B to A, FLAGS set
5EADD A, OUTLoad OUT to B, A PLUS B to A, FLAGS set
5FADD A, INLoad IN to B, A PLUS B to A, FLAGS set
60SUB A, [adr]Load value in address/variable into B, A MINUS B to A, FLAGS set
61SUB A, valLoad value immediately into B, A MINUS B to A, FLAGS set
62SBB A, [adr]Load value in address/variable into B, A MINUS B +CARRY to A, FLAGS set
63SBB A, valLoad value immediately into B, A MINUS B +CARRY to A, FLAGS set
64OR A, [adr]Load value in address/variable into B, A OR B to A
65OR A, valLoad value immediately into B, A OR B to A
66DEC ADecrement A
6BSUB A, BA MINUS B to A, FLAGS set
6CSUB A, PCLoad PC to B, A MINUS B to A, FLAGS set
6DSUB A, DLoad D to B, A MINUS B to A, FLAGS set
6ESUB A, OUTLoad OUT to B, A MINUS B to A, FLAGS set
6FSUB A, INLoad IN to B, A MINUS B to A, FLAGS set
70CMP A, [adr]Load value in address/variable into B, A MINUS B, FLAGS set
71CMP A, valLoad value immediately into B, A MINUS B, FLAGS set
72CMB A, [adr]Load value in address/variable into B, A MINUS B +CARRY, FLAGS set
73CMB A, valLoad value immediately into B, A MINUS B +CARRY to A, FLAGS set
74XOR A, [adr]Load value in address/variable into B, A XOR B to A
75XOR A, valLoad value immediately into B, A XOR B to A
76NOT ANOT A
7BCMP A, BA MINUS B, FLAGS set
7CCMP A, PCLoad PC to B, A MINUS B, FLAGS set
7DCMP A, DLoad D to B, A MINUS B, FLAGS set
7ECMP A, OUTLoad OUT to B, A MINUS B, FLAGS set
7FCMP A, INLoad IN to B, A MINUS B, FLAGS set
90JZ [adr]/labelJump (PC) to address if ZF is set
91JC [adr]/labelJump (PC) to address if CF is set
92JNZ [adr]/labelJump (PC) to address if ZF is not set
93JNC [adr]/labelJump (PC) to address if CF is not set
98JMP [[ptr]]/[var]Jump (PC) to address in ptr/variable
99JMP [adr]/labelJump (PC) to address
9AJMP AJump (PC) to address in A
9BJMP BJump (PC) to address in B
9DJMP DJump (PC) to address in D
9EJMP OUTJump (PC) to address in OUTPUT
9FJMP INJump (PC) to address in IN
AAMOV A, [[ptr]]/[var]Load value in address in ptr/variable into A
ABMOV B, [[ptr]]/[var]Load value in address in ptr/variable into B
ADMOV D, [[ptr]]/[var]Load value in address in ptr/variable into D
AEMOV OUT, [[ptr]]/[var]Load value in address in ptr/variable into OUTPUT
BAMOV [[ptr]]/[var], AStore A in address in ptr/variable
BBMOV [[ptr]]/[var], BStore B in address in ptr/variable
BCMOV [[ptr]]/[var], PCStore PC in address in ptr/variable
BDMOV [[ptr]]/[var], DStore D in address in ptr/variable
BEMOV [[ptr]]/[var], OUTStore OUTPUT in address in ptr/variable
BFMOV [[ptr]]/[var], INStore IN in address in ptr/variable
E0OUT [adr]/varLoad value in address/variable into OUPUT
E1OUT valLoad value immediate into OUTPUT
EAOUT ALoad A into OUTPUT
EBOUT BLoad B into OUTPUT
ECOUT PCLoad PC into OUTPUT
EDOUT DLoad D into OUTPUT
EFOUT INLoad IN into OUTPUT
FCLSTSet LIST-mode PC to MAR/OUTPUT, RAM to OUTPUT)
FEPRGSet PROGRAM-mode PC to MAR/OUTPUT, BUS to RAM/OUTPUT)
FFENDHalt clock
 
 
Logisim implementation
 


 
 
Windows implementation
 


 
 
Schematics
 






















 
Additional files
 
I created a small zipfile with additional material:
- Full logisim implementation
- Full windows implementation
- Spreadsheet with opcodes, microcode and bus spec
- mkRoms app to generate rom-files for control and display
- mac assembler/compiler to generate code from assembler
- sample programs (including Primes.asm)
- Arduino code for nano-programmer

   download (2019/09/20)